The purpose of this lab was to create and test adder circuits, and familiarize

Joe Fortunato
Miriam Mnyuku
B EE 271
Designing and Programming Digital Adder Circuits
Abstract:
The purpose of this lab was to create and test adder circuits, and familiarize the participants with digital
components, wiring digital circuits, working with Quartus Prime Lite and programming an FPGA on a
development board. A circuit was first created using 4 integrated circuit chips with nand, nor, not and xor
gates and a breadboard to create a three-bit adder circuit. The circuit is then constructed in a schematic
diagram and Quartus and tested utilizing a waveform generator. After testing, the program was written in
Verilog and then downloaded to a Field Programmable Gate Array (FPGA) on a DE1-SoC development
board and tested. A four-bit adder was then designed utilizing equations and implemented in Verilog.
The design was then tested with waveforms and downloaded to the development board.
Introduction:
Circuits for adding binary numbers are some of the most basic digital circuits which can be constructed
but are also some of the most important. The first adder circuit should take three binary numbers with two
outputs, a “sum” and a “carry”, which represent the added numbers in two-bit binary.
The second circuit takes four inputs: four one-bit numbers and outputs one three-bit number, which is the
sum of the four inputted numbers.
Materials:
● Altera Terasic DE1-SoC Board with power and USB cables
● Breadboard
● Two LEDs
● Resistors (between 40 and 60 Ohms)
● Jumper wires
● TTL Logic Chips
○ SN74LS86AL – XOR gate chip
○ SN7404AN – Inverter chip
○ SN7402N – NOR gate chip
○ SN7400N – NAND gate chip
● PC with ​Altera Quartus II Lite ​installed
● Keithley Series 2220 Multichannel Programmable DC Power Supply
Procedure:
Part 1: Wiring digital components and LEDs on a breadboard
The first experiment involved wiring an adder circuit design utilizing a breadboard. In lieu of switches,
inputs were connected to ground when pulled to 0 volts and connected to the power rail on the bread
board. A Keithley Series 2220 Multichannel Programmable DC Power Supply was set at 5 volts and
connected to the power and ground rails, the ground rails on each side of the bread board were connected
together to allow access to it on both sides. A circuit was designed utilizing the referenced equations for
the “sum” (Equation 1) and “carry” outputs (Equation 2).
Sum = A B C + A B C + ABC + A B C
Equation 1: Sum
Carry = BC + AC + AB
Equation 2: Carry
The circuit was constructed on the breadboard utilizing the SN74LS86AL XOR gate chip, SN7404AN
inverter chip, SN7402N NOR gate chip, and SN7400N NAND gate chip and jumper wires. The
limitations of the available hardware required that the circuits be built with four or less of each of NAND,
NOR, and XOR gates and five or less inverters. To test the output, LEDs were wired in between the
output of each of the circuits and ground with a resistor with a value of between 40 and 60 Ohms placed
in series between the LED and ground to protect the LED.
Figure 1: Breadboard circuits
Part 2: Creating a schematic diagram and waveforms simulation on Quartus Prime
Quartus was utilized to create a schematic diagram of the circuit prototyped on the breadboard. (Figure 2)
Figure 2: Schematic
Once the schematic was created in Quartus, ModelSim was used to generate a waveform timing diagram
(Figure 3) by overriding the clock for each input. The timing was set to 8.0 microseconds with changes at
one microsecond increments for the inputs. Once the inputs were set, the outputs were generated for the
circuit, and matched with the outputs from the equation and the breadboard, and output waveforms were
generated for the “carry” and “sum” outputs.
Part 3: Verilog and downloading designs to the FPGA
After the design was verified using ModelSim, a new project was created in Quartus. An adder circuit
equivalent to the circuit prototyped on the breadboard was programmed using Verilog HDL in Quartus.
(Code 1: Three-bit adder circuit, Appendix) Input pins were mapped to the inputs and outputs specified in
Table 1 and Table 2.

Input	Pin
A	PIN_AF9
B	PIN_AC12
C	PIN_AB12

Table 1: Input Pins

Output	Pin
Carry	PIN_AF9
Sum	PIN_AC12

Table 2: Output Pins
The Verilog was then compiled and uploaded to the FPGA and tested utilizing switches for inputs A, B
and C and checking the outputs of LEDs which were built into the output pins.
Part 4: Design an adder that adds 4-bits and download it to the FPGA
A four-bit adder circuit was designed to add four 1-bit numbers, this would give a maximum output of
four, so there must be three output LEDs to code for the number four in binary (100). Karnaugh maps
were used to determine a low-cost implementation of the circuits and derive equations to describe the
circuits. The outputs were described using one equation for sum, and two carry outputs (Equation 3: Sum,
Equation 4: Carry, Equation 5: Carry 2). The circuit was then designed and constructed in Verilog, (Code
2: Four-bit adder circuit, Appendix), inputs were set to switches and the outputs were connected to LEDs.
Output was shown by lighting the LEDs for Carry 2, Carry 1 and Sum, which allowed for the binary
representation of numbers from zero (000) to four (100).
Sum = (CD(A⊕B)) ⊕(AB(C⊕D) + A⊕B⊕C⊕D
Equation 3: Sum
Carry 1 = (D(A + B)) ⊕ (C(A⊕B⊕D)) + (A(B⊕CD))
Equation 4: Carry 1
Carry 2 = ABCD
Equation 5: Carry 2

Input	Pin
A	PIN_AF10
B	PIN_AF9
C	PIN_AC12
D	PIN_AB12

Table 3: Four-bit Adder Input Pins

Output	Pin
Sum	PIN_V16
Carry 1	PIN_W16
Carry 2	PIN_V17

Table 4: Four-bit Adder Output Pins
Results:
The breadboard circuit required some troubleshooting due to a transcription error in the initial diagram
drawing, during troubleshooting, voltage recognized as a “1” was approximately 4.8 volts, and as a “0”
was approximately 60 millivolts. After the circuit was corrected, it performed as expected, outputting the
proper binary number at each point. No LEDs were lit when all inputs were routed to ground (0 + 0 =
binary:00 = decimal:0), the “Sum” LED was lit when a single input was powered (0 + 1 + 0 = binary:
01 = decimal: 1), lighting the “Carry” LED when two inputs were powered (1 + 1 + 0 = binary: 10 =
decimal: 2) and lighting both when all three inputs were powered (1 + 1 + 1 = binary: 11 = decimal: 3).
The circuit was input into Quartus as a schematic and then modeled using ModelSim. (Figure 3) The
outputs generated for the circuit, matched with the outputs from the equation and the breadboard in Part 1.
Figure 3: Three-bit adder circuit, schematic implementation
The waveforms show the voltage levels for the different pin inputs and the calculated resulting outputs.
When the waveform shows high, the output voltage would be approximately 5 volts, and when the
waveform shows low, the output is approximately zero volts.
Figure 4: Three-bit adder circuit, Verilog implementation
Figure 5: Four-bit adder circuit
The four-bit adder circuit behaved as expected, outputting 000 when all switches were off, outputting a
the value 001 when one switch was engaged, 010 when two switches were engaged, 011 when three
switches were engaged, and 100 when all four switches were engaged.
Analysis and Conclusion
Overall, the circuits provided a more in-depth understanding of digital circuit design and construction and
allowed for increased familiarity with Verilog and development tools. The use of waveform generators
allowed for prototyping and refinement of code prior to downloading to the physical devices which allows
for more rapid development of digital circuit designs because the designer can test the input and output of
the circuits without needing to download the circuit design to the device.
Appendix:
Code 1: Three-bit adder circuit
Code 2: Four-bit adder circuit

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